d a t a sh eet product speci?cation file under integrated circuits, ic04 january 1995 integrated circuits hef4040b msi 12-stage binary counter for a complete data sheet, please also download: the ic04 locmos he4000b logic family specifications hef, hec the ic04 locmos he4000b logic package outlines/information hef, hec
january 1995 2 philips semiconductors product speci?cation 12-stage binary counter hef4040b msi description the hef4040b is a 12-stage binary ripple counter with a clock input ( cp), an overriding asynchronous master reset input (mr) and twelve fully buffered outputs (o 0 to o 11 ). the counter advances on the high to low transition of cp. a high on mr clears all counter stages and forces all outputs low, independent of cp. each counter stage is a static toggle flip-flop. schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. fig.1 functional diagram. hef4040bp(n): 16-lead dil; plastic (sot38-1) hef4040bd(f): 16-lead dil; ceramic (cerdip) (sot74) hef4040bt(d): 16-lead so; plastic (sot109-1) ( ): package designator north america fig.2 pinning diagram. pinning application information some examples of applications for the hef4040b are: frequency dividing circuits time delay circuits control counters family data, i dd limits category msi see family specifications cp clock input (high to low edge-triggered) mr master reset input (active high) o 0 to o 11 parallel outputs
january 1995 3 philips semiconductors product speci?cation 12-stage binary counter hef4040b msi ac characteristics v ss = 0 v; t amb =25 c; c l = 50 pf; input transition times 20 ns v dd v symbol min. typ. max. typical extrapolation formula propagation delays cp ? o 0 5 105 210 ns 78 ns + (0,55 ns/pf) c l high to low 10 t phl 45 90 ns 34 ns + (0,23 ns/pf) c l 15 35 70 ns 27 ns + (0,16 ns/pf) c l 5 85 170 ns 58 ns + (0,55 ns/pf) c l low to high 10 t plh 40 80 ns 29 ns + (0,23 ns/pf) c l 15 30 60 ns 22 ns + (0,16 ns/pf) c l o n ? o n + 1 5 35 70 ns note 1 (0,55 ns/pf) c l high to low 10 t phl 15 30 ns note 1 (0,23 ns/pf) c l 15 10 20 ns note 1 (0,16 ns/pf) c l 5 35 70 ns note 1 (0,55 ns/pf) c l low to high 10 t plh 15 30 ns note 1 (0,23 ns/pf) c l 15 10 20 ns note 1 (0,16 ns/pf) c l mr ? o n 5 90 180 ns 63 ns + (0,55 ns/pf) c l high to low 10 t phl 40 80 ns 29 ns + (0,23 ns/pf) c l 15 30 60 ns 22 ns + (0,16 ns/pf) c l output transition times 5 60 120 ns 10 ns + (1,0 ns/pf) c l high to low 10 t thl 30 60 ns 9 ns + (0,42 ns/pf) c l 15 20 40 ns 6 ns + (0,28 ns/pf) c l 5 60 120 ns 10 ns + (1,0 ns/pf) c l low to high 10 t tlh 30 60 ns 9 ns + (0,42 ns/pf) c l 15 20 40 ns 6 ns + (0,28 ns/pf) c l fig.3 logic diagram.
january 1995 4 philips semiconductors product speci?cation 12-stage binary counter hef4040b msi note 1. for other loads than 50 pf at the n th output, use the slope given. minimum clock 5 50 25 ns see also waveforms fig.4 pulse width; high 10 t wcph 30 15 ns 15 20 10 ns minimum mr 5 40 20 ns pulse width; high 10 t wmrh 30 15 ns 15 20 10 ns recovery time 5 40 20 ns for mr 10 t rmr 30 15 ns 15 20 10 ns maximum clock 5 10 20 mhz pulse frequency 10 f max 15 30 mhz 15 25 50 mhz v dd v typical formula for p ( m w) dynamic power 5 400 f i +? (f o c l ) v dd 2 where dissipation per 10 2 000 f i +? (f o c l ) v dd 2 f i = input freq. (mhz) package (p) 15 5 200 f i +? (f o c l ) v dd 2 f o = output freq. (mhz) c l = load cap. (pf) ? (f o c l ) = sum of outputs v dd = supply voltage (v) v dd v symbol min. typ. max. typical extrapolation formula
january 1995 5 philips semiconductors product speci?cation 12-stage binary counter hef4040b msi fig.4 waveforms showing propagation delays for mr to o n and cp to o 0 , minimum mr and cp pulse widths.
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